Senior Design Team 17 • Digital ASIC Fabrication

Project Overview

The Computer Engineering undergraduate curriculum’s pedagogy at Iowa State University has been largely based on a theoretical understanding with little emphasis put on hands-on training. While CPRE 381 focuses on building a processor by utilizing software simulation techniques, little insight is gained into how the Register Transfer Language (RTL) can be fabricated into custom hardware. By utilizing fabrication facilities vetted by eFabless, a Google-sponsored company, Dr. Duwe and Dr. Huang have devised a plan to solve this problem by putting senior design teams in charge of creating test Application Specific Integrated Circuit (ASIC) boards to serve as learning frameworks. As our team is the first to serve in this role, we decided to pursue a novel yet effective application extremely relevant to ASICs: Bitcoin Mining. One key component of this application is the hashing process. By working on this implementation, we will accelerate and provide better results for SHA-1 hashing on a small scale.


Team Members

Constantine Mantas

Team Organization Leader

Constantine Mantas is a Computer Engineering major with an interest in hardware design. Through various classwork, internships, and projects, Constantine has gotten experience with various programming languages like Java, C, and Python, and computer hardware design with technologies like ModelSim, Verilog, and VHDL.

Soma Szabo

Component Design

Soma is a Computer Engineering major, pursuing the Master of Engineering concurrent degree program. His classes and work experiences have provided him with knowledge in programming techniques, software languages such as Java, TCL, C/C++, Python, and Dart, as well as hardware description languages such as VHDL and Verilog. He also has experience with computer architecture and related tools such as ModelSim, Vivado, Cadence, and Altium Designer (PCB design).

Courtney Violett

Testing

Courtney Violett is in Computer Engineering. He has worked through a variety of class work and projects, both for class and personal projects, has gained experience in programming languages such as C, Java, HTML, CSS, computer hardware design, and circuit design. He also has experience with tools such as android studio and ModelSim.

Dawood Ghauri

Design Workflow

Dawood is a Computer Engineering major with a minor in Physics. His class experiences have developed his knowledge with respect to programming experiences in C, C++, Java, Python, VHDL, and Verilog.





Weekly Reports

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Bi-Weekly Reports (492)

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Design Documents

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Poster & Final Presentation (492)

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Presentation




Lightning Talks

LT0 - Elevator Pitch
LT1 - Requirements, Constraints, and Engineering Standards
LT2 - Project Plan
LT3 - Design Plan
LT4 - Testing Plan
LTY - YouTube News Report